1. Field of the Invention
The present invention relates to a plasma display panel (PDP), and more particularly, to an apparatus and a method for driving the PDP.
2. Discussion of the Related Art
Flat panel displays, such as a liquid crystal displays (LCD), field emission displays (FED), and PDPs, have been developed recently. Generally, as compared to other flat panel displays, the PDP is brighter, has a higher light emitting efficiency and a wider viewing angle. Thus, the PDP is recognized as a substitute for the conventional cathode ray tube (CRT), especially for large displays of greater than forty inches.
The PDP displays characters or images with plasma generated by gas discharge, and depending upon its size, it may have hundreds of thousands or millions of pixels arranged in a matrix. A PDP is typically classified as a direct current (DC) or an alternating current (AC) type PDP according to its discharge cell structure and driving voltage waveform shape.
The DC PDP has a shortcoming in that current flows in a discharge space when voltage is applied to electrodes in the discharge space, which requires a resistor for restricting the current. To the contrary, the current in the AC DDP is restricted by naturally formed capacitance components, and the electrodes are protected from the impact of ions during discharge because they are covered with a dielectric layer, which results in the AC PDP having a longer lifespan than the DC PDP.
FIG. 1 is a partial perspective view of a conventional AC PDP.
As shown in FIG. 1, pairs of scan electrodes 4 and sustain electrodes 5, covered by a dielectric layer 2 and a protection layer 3, are formed parallel on a first substrate 1. A plurality of address electrodes 8, covered by an insulation layer 7, is formed on a second substrate 6. Barrier ribs 9 are formed in parallel with, and between, the address electrodes 8 on the insulation layer 7. Further, phosphors 10 are formed on the surface of the insulation layer 7 and both sides of the barrier ribs 9. The first substrate 1 and the second substrate 6 are sealed together to form a discharge space 11 between them and in such a manner that the scan electrodes 4 and the sustain electrodes 5 are perpendicular to the address electrodes 8. A portion of the discharge space 11 between a crossing of the address electrode 8 and a pair of the scan electrode 4 and the sustain electrode 5 forms a discharge cell 12.
FIG. 2 shows a tri-electrode plane discharge structure of the PDP.
In such a structure, a discharge for forming a wall charge to select a pixel occurs between an address electrode and a scan electrode, and then a discharge for displaying the image occurs repeatedly for a certain period of time between the scan electrode and the sustain electrode.
A wall charge means a charge formed on a wall, such as at the dielectric layer of a discharge cell, near the respective electrodes and accumulated on the electrodes. Such a wall charge does not actually contact the electrodes, but rather it is described as being “formed”, “accumulated”, or “piled” on the electrodes. Wall voltage means an electric potential difference formed on the wall of the discharge cell by the wall charge.
The barrier ribs form the discharge space and block light generated by a discharge, in order to prevent cross-talk with neighboring pixels. The PDP displays desired colors by making discharges in the pixels, which generate ultra violet rays that excite the phosphors to emit light.
A middle gray level should be realized in order for the PDP to adequately function as a color display, and a method for displaying a middle gray level using time-division control has been used.
FIG. 3 shows a 6 bit gray level realizing method for an AC PDP, in which one TV field is divided to six subfields SF1-SF6, and each of the subfields is further divided into an address period A1-A6 and a display discharge sustain period S1-S6.
However, when using the conventional gray level expressing method with N subfields, a color stripe may occur at low and high gray levels due to excessive unit light.